1. Field of the Invention
The present invention relates to systems employing programmable logic devices and other resources to emulate the behavior of an electronic circuit, and in particular to a circuit board for providing emulation resources for an emulation system.
2. Description of Related Art
A typical digital integrated circuit (IC) employs register transfer logic (RTL) wherein each block of logic within the IC includes an output register for synchronizing state changes in its output signals to edges of a clock signal. An IC designer will usually generate an initial, high-level netlist employing Boolean expressions to characterize each block of logic. The designer will then employ a synthesis tool to convert the high level netlist into a “gate level” netlist describing the logic blocks as sets of interconnected cells, where each cell is a standard IC component such as a transistor or a logic gate. The gate level netlist references each cell instance to be included in the IC by referring to an entry for that cell type in a cell library, a database including an entry for each kind of cell that can be included in an IC. The cell library entry for each cell type describes the internal layout of the cell and includes a model of the cell's behavior. After synthesizing the gate level netlist, the designer employs a placement and routing (P&R) tool to convert the gate level netlist into an IC layout file indicating the position within a semiconductor die of each cell forming the IC and describing how the nets are to be routed between cell terminals. The layout file guides IC fabrication.
An IC designer can use computer-aided simulation and verification tools at each step of the design process to verify that the IC described by the design will behave as expected. For example, to use a circuit simulator, the designer develops a “testbench” incorporating a netlist describing the IC to be simulated and indicating how the IC's input signals are to change state over time. The testbench will also list various signals of the IC to be monitored during the simulation. For gate level netlists, the simulator creates a behavioral model of the IC based on the testbench description of the IC and on behavioral models of the IC's cells obtained from the cell library, and then tests the IC model to determine how the monitored signals would respond to input signal patterns the testbench describes. During the test, the simulator generates a “dump file” containing waveform data representing the time-varying behavior of the monitored signals. The designer can then use various debugging tools to inspect the dump file to determine whether the IC behaved as expected.
Although a simulator can accurately model the behavior of an IC based on either a high-level or gate-level netlist, it can require much processing time to simulate IC behavior. To reduce simulation time a designer can program a simulator to simulate only selected portions of an IC design that are new or have been modified, but this approach may not provide any assurance that the new and old portions of the design will work properly together.
Emulation Systems
Another way to reduce the time needed to verify the IC logic a netlist describes is to use programmable logic devices (PLDs) and other hardware devices to emulate the IC logic. For example U.S. Pat. No. 6,377,911 issued Apr. 23, 2002 to Sample et al, describes a logic emulation system employing field programmable gate arrays (“FPGAs”) that can be programmed to emulate IC logic. Since FPGAs employ high-speed logic gates and other devices to emulate circuit behavior, an emulation system using FPGAs can usually verify IC behavior more quickly than a simulator.
FIG. 1 illustrates a typical prior art emulation system 10 including a set of circuit boards 12 each holding an array of FPGAs 14, each of which can be programmed to emulate the logic of a large number of interconnected logic gates, flip-flops and registers. Each FPGA 14 has many input/output (IO) terminals and many of those IO terminals are linked to IO terminals of other FPGAs 14 on the same circuit board 12 so that the FPGAs can communicate with one another. Since ICs may include large standardized components such as embedded computer processors and memories, emulation system 10 may include processors, memory ICs or other devices mounted on other resource boards 18 for emulating those large IC components. Cable connectors or backplane typically provide signal paths between FPGAs 14 and other resources mounted on resource boards 12 and 18.
When emulator 10 is to act as an in-circuit emulation (“ICE”) system, it emulates an IC within its intended operating environment, installed on a circuit board of an external system so that it can communicate with other devices within that system. A cable 20 links IO terminals of some of FPGAs 14 to a socket of an external system 22 of the type in which the IC being emulated will eventually reside.
To test the emulated IC, an external pattern generator 24 supplies test signal inputs to FPGAs 14 though a probe interface circuit 26 programmed to route the test signals to the appropriate FPGA terminals. A logic analyzer 28 monitors various signals the emulated IC produces through signal paths provided by probe interface circuit 26 provides. A user programs FPGAs 14, pattern generator 24, and probe interface 26 and communicates with logic analyzer 28 through a workstation 30 linked to those devices through a suitable interface circuits 32 such as for example, the workstations serial ports and JTAG bus interfaces.
Resource Interconnections
Each FPGA 14 will have a large number of IO terminals and each circuit board 12 must provide signal paths between the FPGAs and between the FPGAs and external equipment so that they can communicate with one another. FIG. 2 illustrates one prior art approach to routing signals between FPGAs wherein traces on circuit board 12 connect IO terminals of each FPGA 14 to IO terminals of many or all of the other FPGAs 14. Buffers 32 mounted on circuit board 12 buffer signals passing between circuit board 12 and other resource boards and test equipment via cables or motherboard backplane wiring 34. This hard-wired approach to FPGA interconnects is relatively inexpensive, but not very flexible since the number of direct signal paths between each pair of FPGA 14, and between the resource board and other resource boards or test equipment is fixed. In cases where there are no direct signal paths between two FPGAs 14 that are to communicate with one another, or for which there are an insufficient number of direct signals paths, additional signals can be routed through interposing FPGAs, however in such case some of the FPGA resources will be expended on signal routing duties and be unavailable for logic emulation.
FIG. 3 illustrates another prior art approach to signal routing between FPGAs 14 wherein the IO terminals of FPGAs 14 and the external signal buffers 32 all communicate through a switching matrix 34, such as a crosspoint switch, mounted on circuit board 12. The switch matrix approach provides more flexible routing than the fixed routing of FIG. 2 because it allows any FPGA terminal to directly communicate within any other FPGA terminal or any external resource. But since the number of signal paths switch matrix 34 must provide is proportional to the square of the number of FPGA terminals and buffered signal paths to be interconnected, the necessary switch matrix size becomes impractically large for a circuit board having a large array of FPGAs, each having a large number of IO terminals.
What is needed is an emulation resource board for holding PLDs and other resources and for flexibly routing signals between the PLDs on the resource board and between those PLDs and resources mounted on other resource boards, computers and other external equipment at a reasonable cost and without having to use the FPGA resources signal routing. The resource board should also provide the logic and balanced signal paths needed to deliver clock signals to the PLDs. It would also be helpful to reduce the number of signals needed to communicate with external equipment by implementing much of the pattern generation and data acquisition functionality needed to test an emulated circuit on the resource board itself.